FIG. 1 is a simplified diagram of a PRML (Partial Response Maximum Likelihood) system 1 usable in connection with reading information from a hard disk. PRML system 1 includes a variable gain amplifier 2, an equalizer 3, an analog-to-digital converter 4, a timing and gain recovery circuit 5 and a maximum likelihood detector 6. A head (not shown) moving over the surface of a magnetic media on the hard disk surface outputs a signal. This signal is amplified by a preamplifier (not shown) and is supplied to the variable gain amplifier 2 via input 7.
PRML system 1 involves a timing control loop (including analog-to-digital converter 4 and timing and gain recovery circuit 5) which controls the analog-to-digital converter to take samples of the input signal at the correct times in accordance with the partial response scheme used (PR4, EPR4 and E.sup.2 PR4 are partial response schemes). PRML system 1 also involves an automatic gain control loop (including variable gain amplifier 2, equalizer 3, analog-to-digital converter 4, and timing and gain recovery circuit 5) which maintains the correct amplification level in the system. In general, the gain of the variable gain amplifier is controlled via input 8 so that an input signal of maximum amplitude under normal operating conditions on input 7 does not result in the analog-to-digital converter outputting its maximum digital value on output 9. Rather, analog-to-digital converter "headroom" is reserved so that the gain control loop can detect a high signal level and reduce loop gain accordingly before the signal is clipped. Equalizer 3 functions to reshape the input pulses of the input signal in accordance with the partial response scheme employed. Maximum likelihood detector 6 (for example, a Viterbi detector) receives the samples from the analog-to-digital converter and determines the input pattern most consistent with the observed samples. This determined most likely input pattern is output in the form of a stream of digital values on the output 10 of the maximum likelihood detector 6.
The maximum likelihood detector 6 is typically quite complex. Accordingly, techniques are sought for reducing the complexity (and therefore size as implemented in integrated circuit form) of the maximum likelihood detector in a PRML system.